As the first National Science Foundation (NSF) Engineering Research Center at Georgia Tech, the Georgia Tech PRC is a unique Global Center which has pioneered an integrated approach to cross-discipline research and education, and global industry collaborations. This visionary approach was a decade ahead of the recognized need for this type of collaborative research center. PRC employs the most comprehensive and leading-edge research utilizing three types of industry research programs – each involving academic and research faculty, graduate and undergraduate students as well as industry mentors, in partnership with 80 global companies.
The Center for Compound Semiconductors (CCS) is a focal point for research and educational collaborations in the Georgia Tech community related to compound semiconductors, including conventional and nanotechnology materials and devices.
The Center for Micro Electro-Mechanical Systems (MEMS) & Microsystems Technology (CMMT) serves as a central entity for MEMS research and educational activities across various disciplines of engineering at the Georgia Institute of Technology.
Located in the Technology Square Research Building and operated by the Georgia Electronic Design Center, are a variety of RF, mm-wave and photonics test beds and testing facilities. Including the capability of providing very high-precision semiconductor active/passive device/circuits characterization including DC~170 GHz small-signal s-parameters and dedicated load-pull systems up to 110 GHz. Other capabilities include spectrum analysis up to 170 GHz and noise figure measurements up to 28 GHz.
The GTRI Microelectronics and Nanotechnologies Laboratory (GTRI-MNL) conducts microelectronics and nanotechnology research on compound semiconductors that include gallium arsenide (GaAs) and gallium nitride (GaN). Molecular beam epitaxy (MBE) is our main semiconductor growth technique.
The mission of the Center is to improve the fundamental understanding of the science and technology of advanced PV devices, to fabricate record high efficiency solar cells, to provide training and enrich the educational experience of students in this field, and to give the U.S. a competitive edge by providing guidelines to industry and DOE for achieving the cost effective and high efficiency PV devices.
The Center for Co-design of Chip, Package, System conducts leading-edge research in the following areas:
• System Architecture, Planning, Modeling and Implementation
• IC Floor Planning, Place & Route, Design, Modeling and Characterization
• Advanced Packaging, Substrate Fabrication, Modeling and Characterization
• Advanced Interconnect and 3D Integration Technologies
• Electronic Design Automation that includes Physical CAD and Multi-physics Modeling
• Emerging Device and Interconnect Technologies
The center is organized into program specific areas where a group of faculty with complimentary expertise work on application driven technologies.
The National Nanotechnology Coordinated Infrastructure (NNCI), supported by the National Science Foundation (NSF), is an integrated networked partnership of user facilities serving the needs of nanoscale science, engineering, and technology. The NNCI is a research facilitator, providing state-of-the-art equipment, resources, staff expertise, and training to enable high-quality nanoscale research. These user facilities are open to researchers from academia, industry, and government. To learn more, please visit www.nnci.net.